Title :
A sub-50 psec. 89 K gate ECL-gate array with 480 Kb BiCMOS STRAM
Author :
Tago, Shusei ; Matsumoto, Naoya ; Kaga, Hiroshi ; Ogawa, Tadahiko ; Ohkawa, Shin-Ichi ; Kobayashi, Masaharu
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
A sub-50-ps low power ECL sea of cells gate array family with embedded high-speed/high-density BiCMOS self-timed RAM (STRAM) is described. The applied process technology has realized a maximum cut-off frequency of 23-GHz double polysilicon self-aligned bipolar transistor, 0.5-μm triple-well CMOS transistor, and a maximum of five layers of Au metallization. An unloaded gate delay time of 36 ps with high-drive capability has been achieved using a novel active-pull-down emitter follower
Keywords :
BiCMOS memory circuits; application specific integrated circuits; emitter-coupled logic; logic arrays; random-access storage; very high speed integrated circuits; 0.5 micron; 23 GHz; 36 ps; 480 kbit; Au metallisation; BiCMOS STRAM; ECL-gate array; Si; active-pull-down emitter follower; double polysilicon self-aligned bipolar transistor; embedded; high-density; high-drive capability; high-speed; low power; maximum cut-off frequency; sea of cells gate array; self-timed RAM; triple-well CMOS transistor; unloaded gate delay time; BiCMOS integrated circuits; Circuit testing; Clocks; Delay effects; Driver circuits; Energy consumption; Gold; National electric code; Read-write memory; Voltage;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410835
