Reliability investigations of large die wafer level packages: Optimization of package structure and materials to improve board level reliability

Wafer level packaging (WLP) of electronic components has become increasingly popular in recent years. The WLP package has the same foot print as the die and is therefore the smallest package possible. This is important for applications where maximum functionality is required in a small space, especially for mobile devices. The largest package sizes and pin counts used for WLP components have steadily increased in recent years. As the mechanical stresses in WLP packages increase with die size as well, board level reliability becomes a major concern. As such, the questions arise: what is the maximum die size possible for a WLP to meet board level reliability requirements and, for a given package size, how can the board level reliability be improved? To start to answer these questions, we have designed a large die test vehicle based on a dummy wafer (8×8 mm in size with 444 connections at 0.4mm pitch) with features in the package that are common to devices in production today, such as redistribution traces, polymer passivation layers, under bump metallization, and solder balls for interconnection to the test board. Using wafer level processes, we have assembled the test vehicles under different conditions in a design of experiment. We varied the parameters of polymer passivation thickness, redistribution trace thickness, and final die thickness and then characterized the board level reliability under temperature cycling and drop test conditions for a statistically significant sample size.