Title :
A datapath compiler library for 0.7μm CMOS
Author_Institution :
Compass Design Autom., San Jose, CA, USA
Abstract :
A rich library of custom datapath functions has been developed for a 0.7-μm Leff CMOS process, scalable to 0.55-μm Leff. A well-balanced clock scheme, good power distribution mesh and optional ability to efficiently use a third layer of metal lend this library to high-performance applications. The library is well integrated into datapath compilation, datapath synthesis, chip estimation, and HDL generation tools
Keywords :
CMOS logic circuits; application specific integrated circuits; cellular arrays; circuit analysis computing; circuit layout CAD; hardware description languages; logic CAD; logic arrays; network routing; 0.7 micron; CAD; CMOS process; HDL generation tools; Verilog; chip estimation; clock scheme; custom datapath functions; datapath compiler library; datapath synthesis; gate array; high level VHDL; high-performance applications; logic simulation models; multi-bit logic design; optional ability; power distribution mesh; semicustom netlist; standard cell; Capacitance; Clocks; Feeds; Geometry; Libraries; Logic design; Power grids; Routing; Signal generators; Variable structure systems;
Conference_Titel :
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-1375-5
DOI :
10.1109/ASIC.1993.410837
