Speed Enhanced Mixed Signal Design-for-Test Using Hybrid Fault Based Testing Algorithms

Design-For-Test is any method of improving the testability of a circuit by design. In this paper we have proposed two algorithms for mixed signal testing which to the best of our knowledge is not proposed elsewhere as per our literature survey conducted. The first is called Sequential Search based test sequence generation algorithm used for generating optimum test sequence for the circuit under test (CUT). The second is called hybrid fault based testing algorithm used for detecting both parametric and catastrophic faults which uses optimized sequence generated by the first algorithm as the input. The Figure of Merit (FOM) for the first algorithm gives the measure of all the faults for a particular test and FOM for the second algorithm gives the measure of all the tests for a particular circuit. The major challenges in the mixed signal test arena includes limited IEEE approved EDA tools having multidomain modeling and simulation features, standard fault models for mixed signal circuits, high costs of the EDA tool and lack of structured test methodology which is universally adopted as in the case of digital circuits. The proposed methodology also uses techniques like behavioral modeling of fault-free and faulty circuit blocks using VHDL-AMS, fault collapsing & concurrent application of input test sequence for achieving reduction in total test time and cost. The performance analysis of the newly proposed algorithms were done using RLC Ladder circuit used as the CUT. A comparison of the proposed algorithms were done with the previous researches in the same field.