A cost effective method for TSV backside reveal

Through Silicon Via (TSV) can be used to increase interconnect bandwidth, reduce wire delay due to shorter vertical signal path, and improve power efficiency ^[1-3]. Via Reveal-a kind of wafer back side process moduleplays an important role in the successful implementation of TSV. In via-first and via-mid TSV integration flows, Si must be removed from the backside of the wafer to make contact with the bottom of the TSVs. This operation is performed using a mechanical grind followed by a reveal etching process. So in this paper, we will focus on the TSV reveal unit process. Firstly, we will briefly review TSV integration technology; Then a set of experiments is described which were used to select etch parameters to achieve the desired etching rate, selectivity and profile. Lastly we will show the results of TSV reveal using wet etching process. The proper composition of the HNO₃/HF/CH₃COOH(HNA) solutions, etching parameter, and TEOS deposited by proper temperature provide the necessary process control and etching selectivity that enable the use of higher throughput wet etch for TSV back etch.