Arithmetic logic circuits using self-timed bit level dataflow and early evaluation

A logic style known as Phased Logic (PL) is applied to arithmetic circuits. Phased logic is a dual-rail LEDR logic style that allows automatic translation from a clocked netlist to a self-timed implementation. Bit level dataflow, early evaluation and automatic filtering of transient computations within PL circuits can lead to both increased performance and higher energy efficiency than the original clocked netlist. Simulation results for a 16×16 iterative multiplier based on a LUT4 design show a 23% speed improvement and 20% energy improvement over the clocked design. A Y=Y@1*a +b calculation using an array multiplier design shows a 15% performance decrease but is 2× more energy efficient than the clocked counterpart