Title :
Reduced access time with WTA sense amplifier for standard CMOS SRAM cell
Author :
Basak, D. ; Baishnab, K.L. ; Joseph, Friedel
Author_Institution :
Dept. EEE, Indian Inst. of Technol. Guwahati, Guwahati, India
Abstract :
In this paper we employed Winner Take All (WTA) circuit for sensing the bit line capacitance. It is an important block in hardware realization of neural networks. The property of a neural logic of selection of the highest intensity signal amongst competing signals highly fits for our design of amplifying the voltage difference between bit lines quickly. A comparative study is done to show the better performance of our proposed design compared to the conventional cross-coupled amplifier. The design and simulation is carried out in Cadence virtuoso platform with UMC 0.18μm process technology.
Keywords :
CMOS memory circuits; SRAM chips; amplifiers; neural chips; Cadence virtuoso platform; UMC process technology; WTA sense amplifier; bit line capacitance; cross-coupled amplifier; hardware realization; highest intensity signal; neural logic property; neural networks; reduced access time; size 0.18 mum; standard CMOS SRAM cell; winner take all circuit; CMOS integrated circuits; Capacitance; Equations; Mathematical model; Random access memory; Sensors; Transistors; Neural network and Cross-coupled gate; Sense amplifier; WTA;
Conference_Titel :
Advances in Electrical Engineering (ICAEE), 2014 International Conference on
Conference_Location :
Vellore
DOI :
10.1109/ICAEE.2014.6838463
