DocumentCode
1602111
Title
An ECL gate array with 2.5 GHz embedded PLL
Author
Yuen, Clement K. ; Yung, Y.S. ; Rara, G. ; Lalchandani, A. ; Lam, N.C. ; Ng, T. ; Tso, R.
Author_Institution
National Semiconductor, Santa Clara, CA, USA
fYear
1993
Firstpage
199
Lastpage
202
Abstract
Utilizing National Semiconductor´s 0.8 μm ABiC IV BiCMOS process, an ECL gate array with an embedded PLL has been developed specifically for communication applications, e.g., SONET and fiber channel interface. The PLL can be programmed up to 2.5 GHz. Together with 1400 ECL gates, the array can be used to implement either serial-to-parallel or parallel-to-serial conversion functions up to SONET STS-48 interface
Keywords
BiCMOS digital integrated circuits; BiCMOS logic circuits; FDDI; SONET; application specific integrated circuits; digital phase locked loops; emitter-coupled logic; logic arrays; network interfaces; optical fibre LAN; 0.8 micron; 2.5 GHz; ABiC IV BiCMOS process; ECL gate array; SONET; embedded PLL; fiber channel interface; parallel-to-serial conversion; serial-to-parallel conversion; Charge pumps; Clocks; Filters; Frequency synthesizers; Phase detection; Phase frequency detector; Phase locked loops; SONET; Switches; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-1375-5
Type
conf
DOI
10.1109/ASIC.1993.410839
Filename
410839
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