Tuning the noise margins of gate-all-around MOSFET based inverters through non-circular multi-channel architecture

Gate-all-around (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs) are high priority research topics of the present day. The ability to increase the drive current through a multi-channel (MC) architecture is a unique feature in GAA devices. Limitations in the fabrication process may result in non-circular cross-section of GAA MOSFETs. The most practical approach is the elliptical cross-section which is characterized by a geometry aspect ratio (AR) defined as the ratio of major and minor axes. In this paper, we have investigated the effects of AR and MC architectures on the noise margins (NMs) (high and low) of MC GAA MOSFET based CMOS inverters. We have developed a simulator which can faithfully plot the voltage-transfer characteristics (VTC) of such circuits. Analytical equations have been presented to model the NMs. To judge the reliability of our model, we have validated the same with reported experimental data and the average deviation obtained was within 1.2% (NMH) to 5.1% (NML). Our analysis has also been extended to explore the possibilities of enhancing the circuit performance by using high-k materials.