• DocumentCode
    1602459
  • Title

    COREL: a dynamic compaction procedure for synchronous sequential circuits with repetition and local static compaction

  • Author

    Pomeranz, Irith ; Reddy, Sudhakar M.

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
  • fYear
    2001
  • fDate
    6/23/1905 12:00:00 AM
  • Firstpage
    142
  • Lastpage
    147
  • Abstract
    We propose a dynamic compaction procedure for non-scan synchronous sequential circuits. The procedure combines four compaction techniques. (1) Dynamic ordering of test subsequences generated for yet-undetected faults. (2) Local static compaction is performed every time a new subsequence is added to the test sequence. (3) Short test subsequences are discarded to prevent them from increasing the test length unnecessarily. (4) The test generation process is repeated with a fault order dynamically determined based on the existing test sequence. With these techniques, dynamic compaction yields test lengths that are shorter than all but the most aggressive and computationally expensive static compaction procedure
  • Keywords
    VLSI; logic testing; sequential circuits; COREL; dynamic compaction procedure; dynamic ordering; fault order; local static compaction; nonscan circuits; repetition; synchronous sequential circuits; test generation process; test sequence; test subsequences; Circuit faults; Circuit testing; Cities and towns; Compaction; Computational complexity; Concatenated codes; Fault detection; Performance evaluation; Sequential analysis; Sequential circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on
  • Conference_Location
    Austin, TX
  • ISSN
    1063-6404
  • Print_ISBN
    0-7695-1200-3
  • Type

    conf

  • DOI
    10.1109/ICCD.2001.955016
  • Filename
    955016