Title :
A partitioning and storage based built-in test pattern generation method for synchronous sequential circuits
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
We describe a built-in test pattern generation method for synchronous sequential circuits based on partitioning and storage of test subsequences. Under this method, a set of subsequences Ψ is stored on-chip. On-chip test sequences are obtained by implementing a subset of the Cartesian product ΨxΨx···xΨ. The set Ψ is obtained by iterative partitioning of a precomputed test sequence T. The number of subsequences in Ψ is minimized at every iteration in order to reduce the final storage requirements, the test application time, and the computational effort required to produce the final set Ψ
Keywords :
VLSI; built-in self test; computational complexity; fault simulation; logic partitioning; logic testing; sequential circuits; Cartesian product; built-in test pattern generation method; iterative partitioning; on-chip test sequences; storage requirements; synchronous sequential circuits; Built-in self-test; Circuit faults; Circuit testing; Cities and towns; Electrical fault detection; Fault detection; Sequential analysis; Sequential circuits; Synchronous generators; Test pattern generators;
Conference_Titel :
Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-7695-1200-3
DOI :
10.1109/ICCD.2001.955017
