DocumentCode
1602648
Title
High speed differential I/O overview and design challenges on Intel enterprise server platforms
Author
Beom-Taek Lee ; Mazumder, M. ; Mellitz, R.
Author_Institution
Intel Corp., Santa Clara, CA, USA
fYear
2011
Firstpage
779
Lastpage
784
Abstract
In this paper, the high speed differential I/O buses which are used on Intel server platforms are explored. The characteristics of channel components are examined along with channel and I/O circuit design challenges. Statistical time domain and frequency domain methods are briefly discussed as start-of-art simulation tools.
Keywords
high-speed integrated circuits; integrated circuit design; network servers; system buses; I/O circuit design challenges; Intel enterprise server platforms; Intel server platforms; channel components; frequency domain methods; high speed differential I/O buses; high speed differential I/O overview; statistical time domain method; Crosstalk; Jitter; Servers; Signal to noise ratio; Sockets;
fLanguage
English
Publisher
ieee
Conference_Titel
Electromagnetic Compatibility (EMC), 2011 IEEE International Symposium on
Conference_Location
Long Beach, CA, USA
ISSN
2158-110X
Print_ISBN
978-1-4577-0812-1
Type
conf
DOI
10.1109/ISEMC.2011.6038414
Filename
6038414
Link To Document