Gate sizing to eliminate crosstalk induced timing violation

Digital circuits manufactured in deep sub-micron technologies may experience crosstalk-induced delay and noise signals. Crosstalk-induced delay can be quite significant and sensitive to the driver strength of coupling neighbors. In this paper, we propose gate-sizing techniques to reduce delay in presence of crosstalk effects. The techniques are based on our (2001) previously proposed crosstalk aware static timing analysis. Our experiments show that the proposed techniques are effective and may help designers achieve faster timing closure.