Design of testable storage/logic arrays

Author

Bucknell, Mary S. ; Fuchs, W. Kent ; Savin, Howard V.

Author_Institution

Coord. Sci. Lab., Illinois Univ., Urbana, IL, USA

fYear

1988

Firstpage

209

Abstract

Storage/logic arrays (SLAs) represent an efficient structured logic array approach to the design of VLSI sequential logic circuits with low area overhead. The authors present an approach to testable SLA design which provides for detection of all missing device and stuck-at faults in addition to several broader classes of faults, including bridging and open line faults. Testable designs and test generation algorithms are given for both NMOS and static CMOS SLAs. An SLA augmented for testability is presented. The hardware costs are analyzed and the testing strategy is presented. The test sets are analyzed and are shown to provide high fault coverage over a large class of faults.<>

Keywords

VLSI; field effect integrated circuits; integrated circuit testing; logic arrays; logic design; logic testing; sequential circuits; NMOS arrays; VLSI sequential logic circuits; bridging faults; hardware costs; high fault coverage; low area overhead; open line faults; static CMOS arrays; structured logic array approach; stuck-at faults; test generation algorithms; testable storage/logic arrays; testing strategy; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Logic arrays; Logic design; Logic devices; Logic testing; Sequential circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1988., IEEE International Symposium on

Conference_Location

Espoo, Finland

Type

conf

DOI

10.1109/ISCAS.1988.14904

Filename

14904