Statistical link analysis and in-situ characterization of high-speed memory bus in 3D package systems

High-speed link design in a 3D package system poses unique challenges due to the fact that it provides limited visibility to signal quality and that supply noise induced jitter is large due to a poor power distribution network in a small form factor. This paper outlines a statistical link simulation flow to accurately capture the impact of timing jitter due to power supply noise in 3D systems. The analysis includes on-chip jitter accumulation and link-level jitter tracking by considering both passive channel and on-chip signal path. On-chip measurement techniques which allow in-situ testing of the overall link margin are also described.