DocumentCode
1602749
Title
A new strategy of performance-directed technology mapping algorithm for LUT-based FPGAs
Author
Chen, K.N. ; Wang, T.S. ; Lai, Y.-T.
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Volume
4
fYear
1996
Firstpage
822
Abstract
In this paper we present a new strategy of performance-directed technology mapping algorithm for LUT-based FPGAs to minimize both CLB levels on critical paths and total wire length. We first use a clustering approach to get a level-optimized mapping solution. Then we use a min-cut based block pairing algorithm to minimize the total wire length and the number of used CLBs. Experimental results on the MCNC benchmark circuits show that our algorithm is effective
Keywords
field programmable gate arrays; LUT-based FPGA; clustering approach; level-optimized mapping solution; min-cut based block pairing algorithm; performance-directed technology mapping algorithm; total wire length minimisation; Application specific integrated circuits; Clustering algorithms; Delay; Field programmable gate arrays; Integrated circuit interconnections; Minimization methods; Programmable logic arrays; Prototypes; Wires; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location
Atlanta, GA
Print_ISBN
0-7803-3073-0
Type
conf
DOI
10.1109/ISCAS.1996.542151
Filename
542151
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