Title :
On the micro-architectural impact of clock distribution using multiple PLLs
Author :
Saint-Laurent, Martin ; Swaminathan, Madhavan ; Meindl, James D.
Author_Institution :
Intel Corp., Austin, TX, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
Clock distribution has traditionally been a circuit design problem with negligible micro-architectural impact. However, for clock distribution networks using multiple phase-locked loops (PLLs), this will most likely not be the case. This paper discusses the micro-architectural impact of using multiple PLLs for clock distribution. Two PLL phase synchronization algorithms are presented and analyzed. They are compared in terms of efficiency, performance, and complexity. For both, the micro-architectural impact is small, but certainly not negligible
Keywords :
clocks; computer architecture; phase locked loops; PLL phase synchronization; clock distribution architecture; clock distribution networks; micro-architectural impact; multiple phase-locked loops; Algorithm design and analysis; Circuit synthesis; Clocks; Cutoff frequency; Design for testability; Feedback; Frequency synchronization; Integrated circuit interconnections; Jitter; Phase locked loops;
Conference_Titel :
Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-7695-1200-3
DOI :
10.1109/ICCD.2001.955031
