DocumentCode
1602930
Title
Identifying redundancies using reduced symbolic simulation [digital VLSI circuits]
Author
Mathew, Ben ; Saab, Daniel G.
Author_Institution
MIPS Technol. Inc., Silicon Graphics Comput. Syst., Mountain View, CA, USA
Volume
4
fYear
1996
Firstpage
826
Abstract
Redundancies are introduced in digital VLSI circuits due to immature synthesis techniques. Test generation algorithms have problems in handling them as well. Redundancy identification becomes important as a result. This paper presents a redundancy identification algorithm that does not rely on branch-and-bound search techniques. It utilizes a reduced form of symbolic simulation and contains several new techniques to aid in this process. Results are presented on the ISCAS circuits
Keywords
VLSI; circuit analysis computing; digital integrated circuits; identification; redundancy; symbol manipulation; digital VLSI circuits; reduced symbolic simulation; redundancy identification algorithm; Automatic test pattern generation; Circuit faults; Circuit simulation; Circuit synthesis; Circuit testing; Fault diagnosis; Logic; Redundancy; Silicon; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location
Atlanta, GA
Print_ISBN
0-7803-3073-0
Type
conf
DOI
10.1109/ISCAS.1996.542152
Filename
542152
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