High performance parallel fault simulation

Parallel simulation on multiple processors is one method by which fault simulation time in large circuits can be reduced significantly. To realize near-linear execution time gains from parallel processing, the parallelization techniques used should result in an even computational load distribution across the processors in the parallel system. Fault simulation can be parallelized either by partitioning the set of faults, the set of vectors or both. We develop a fault partitioning technique for parallel simulation. The technique is applied to a commercial fault simulator from IBM. Most previous efforts at multiprocessor fault simulation have been validated on small publicly-available benchmark circuits. Our methods are validated on a large circuit with over a million faults. Our partitioning techniques result in a uniform load distribution on this circuit over a range of partitions, from one with 4 blocks to one with 12 blocks. In each case, the partitioning technique is quantifiably superior to random partitioning, by an order of magnitude. We also develop techniques to effectively combine fault-parallel arid vector-parallel multiprocessor simulation. This combined approach results in better execution time when compared to using each approach individually