Fault models´ analysis at register-transfer level description

The proliferation of system-on-chip designs is forcing us to consider the possibility of doing all design phases at the highest possible levels of abstraction. Behavioral-level design tools are today commercially available, and offer a solution to this problem. Conversely, test issues are usually addressed at the lowest levels of abstraction and, although in recent years many efforts have been devoted to the definition of strategies for addressing test at the high level, a global solution is yet to come. We present preliminary experimental results about some of the available high-level fault models working at the register-transfer (RT) level. The experimental procedure we adopted is presented and some preliminary results are discussed.