• DocumentCode
    160319
  • Title

    A low power BIST scheme based on block encoding

  • Author

    Tian Chen ; Liuyang Zheng ; Wei Wang ; Fuji Ren ; Xishan Zhang ; Hao Chang

  • Author_Institution
    Sch. of Comput. & Inf., Hefei Univ. of Technol., Hefei, China
  • fYear
    2014
  • fDate
    11-13 July 2014
  • Firstpage
    1
  • Lastpage
    7
  • Abstract
    With the development of integrated circuit manufacturing technology, low power test has become a focus of concern during testing fields. This paper proposes a new low power BIST (built-in self test) scheme based on block encoding which first exploit a block re-encoding method to optimize the test cube, and then a low power test based on LFSR (linear feedback shift register) reseeding is applied. According to the compatibility of flag, the scheme proposes a grouping algorithm based on flag to divide and reorder the test cubes in the test cube set. Experimental results show that the scheme not only obtain better test compression ratio and test data storage, but also reduce the test power consumption effectively.
  • Keywords
    built-in self test; encoding; integrated circuit testing; low-power electronics; block encoding; built-in self test scheme; grouping algorithm; integrated circuit manufacturing technology; low power BIST scheme; low power test; test compression ratio; test data storage; test power consumption; Circuit faults; Clocks; Encoding; Hardware; Merging; Power demand; Vectors; LFSR reseeding; low power test; test cube block; test data compression;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computing, Communication and Networking Technologies (ICCCNT), 2014 International Conference on
  • Conference_Location
    Hefei
  • Print_ISBN
    978-1-4799-2695-4
  • Type

    conf

  • DOI
    10.1109/ICCCNT.2014.6963020
  • Filename
    6963020