• DocumentCode
    1603193
  • Title

    Fixed-outline floorplanning through better local search

  • Author

    Adya, Saurabh N. ; Markov, Igor L.

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
  • fYear
    2001
  • fDate
    6/23/1905 12:00:00 AM
  • Firstpage
    328
  • Lastpage
    334
  • Abstract
    We study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SOCs. We empirically show that the fixed-outline floorplan problem instances are significantly harder than the well-researched instances without fixed outline. Furthermore, we suggest new objective functions to drive simulated annealing and new types of moves that better guide local search in the new context. Our empirical evaluation is based on a new floorplanner implementation Parquet-1 that can operate in both outline free and fixed-outline modes. Our proposed moves are based on the notion of floorplan slack. The proposed slack computation can be implemented with all existing algorithms to evaluate sequence pairs, of which we use the simplest, yet semantically indistinguishable from the fastest reported. A similar slack computation is possible with many other floorplan representations. In all cases, the slowdown is by a constant factor - roughly 2x
  • Keywords
    circuit layout CAD; search problems; simulated annealing; floorplanning; local search; sequence pair representation; simulated annealing; slack-based moves; Application specific integrated circuits; Computational modeling; Context modeling; Modems; Pins; Routing; Shape; Simulated annealing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on
  • Conference_Location
    Austin, TX
  • ISSN
    1063-6404
  • Print_ISBN
    0-7695-1200-3
  • Type

    conf

  • DOI
    10.1109/ICCD.2001.955047
  • Filename
    955047