Masking and etching of silicon and related materials for geometries down to 25 nm

This paper describes a technique to generate structures down to 25 nm in width on top of a silicon wafer, applying layer deposition and anisotropic dry etching processes. Due to the excellent homogeneity and reproducibility of the CVD deposition techniques, feature size control and homogeneity is superior over a whole wafer lot. Minimum feature size achieved up to now is 25 nm in linewidth. All MOS type materials like polysilicon, silicon oxide and nitride, aluminum, titanium nitride and tungsten were etched with dimensions down to 100 nm or below. The structure definition technique is transferable to any technology line, because only standard process steps like CVD deposition, dry and wet etching, and conventional optical lithography are necessary