Title :
Three versions of a digital hardware implementation of a multi-layer perceptron in 0.7 μ CMOS-design
Author :
Tryba, V. ; Kiziloglu, B.
Author_Institution :
SIBET GmbH, Hannover, Germany
Abstract :
In this paper, three versions of an implementation of a multi-layer perceptron as a neural ASIC are presented. A fully parallel version with 9 neurons as a fast version, a version with sequential processing inside the neurons, and a version with one fast neuron which is multiplexed. The three versions are compared in size and speed
Keywords :
CMOS integrated circuits; application specific integrated circuits; cellular neural nets; multilayer perceptrons; neural chips; 0.7 μ CMOS-design; 0.7 mum; digital hardware implementation; multilayer perceptron; neural ASIC; sequential processing; Adders; Application specific integrated circuits; Backpropagation; Costs; Hardware; Integrated circuit layout; Multilayer perceptrons; Neurons; Registers; Sensor systems;
Conference_Titel :
Cellular Neural Networks and their Applications, 1996. CNNA-96. Proceedings., 1996 Fourth IEEE International Workshop on
Conference_Location :
Seville
Print_ISBN :
0-7803-3261-X
DOI :
10.1109/CNNA.1996.566607
