• DocumentCode
    1603392
  • Title

    Superscalar extension for the MULTRIS processor

  • Author

    Nair, Unnikrishnan R. ; Quammen, Donna J. ; Tabak, Daniel

  • Author_Institution
    Cornet Inc., Springfield, VA, USA
  • fYear
    1997
  • Firstpage
    482
  • Lastpage
    486
  • Abstract
    The MULTRIS (MULTitasking RISC) is a RISC-type processor developed at George Mason University and targeted for multitasking languages. The paper extends the previous design of the GMU MULTRIS processor, by providing it with a deeper pipeline and with instruction level parallelism (ILP) capability. The design is modified for several versions of superscalar operation: two-issue, three-issue, and four-issue. A detailed design extension for the above options is presented and discussed. A significant improvement in performance, compared to the earlier design can be attained.
  • Keywords
    microprocessor chips; multiprogramming; parallel architectures; performance evaluation; pipeline processing; reduced instruction set computing; George Mason University; MULTRIS processor; RISC; design extension; instruction level parallelism; multitasking languages; performance; pipeline; superscalar extension; Costs; Decoding; Hardware; Hazards; History; Logic testing; Microprocessors; Modems; Pipelines; Reduced instruction set computing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    EUROMICRO 97. New Frontiers of Information Technology., Proceedings of the 23rd EUROMICRO Conference
  • Conference_Location
    Budapest, Hungary
  • ISSN
    1089-6503
  • Print_ISBN
    0-8186-8129-2
  • Type

    conf

  • DOI
    10.1109/EURMIC.1997.617360
  • Filename
    617360