Realization of multiple-output functions by reconfigurable cascades

Author

Iguchi, Yukihiro ; Sasa, Tsutomu ; Matsuura, Munehiro

Author_Institution

Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

388

Lastpage

393

Abstract

A realization of multiple-output logic functions using a RAM and a sequencer is presented. First, a multiple-output function is represented by an encoded characteristic function for non-zeros (ECFN). Then, it is represented by a cascade of look-up tables (LUTs). Finally, the cascade is simulated by a RAM and a sequencer. Multiple-output functions for benchmark functions are realized by cascades of LUTs, and the number of LUTs and levels of cascades are shown. A partition method of outputs for parallel evaluation is also presented. A prototype has been developed by using RAM and FPGA. This realization uses time domain multiplexing, and is useful for the case where the number of output pins is limited

Keywords

binary decision diagrams; combinational circuits; field programmable gate arrays; logic partitioning; multivalued logic circuits; random-access storage; reconfigurable architectures; FPGA; RAM; encoded characteristic function; look-up tables; multiple-output logic functions; output pins; parallel evaluation; partition method; reconfigurable cascades; sequencer; time domain multiplexing; Binary decision diagrams; Computer science; Field programmable gate arrays; Logic functions; Logic programming; Programmable logic arrays; Read-write memory; Reconfigurable architectures; Reconfigurable logic; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-7695-1200-3

Type

conf

DOI

10.1109/ICCD.2001.955056

Filename

955056