Interconnect-centric array architectures for minimum SRAM access time

Author

Bhavnagarwala, Azeez J. ; Kosonocky, Stephen ; Meindl, James D.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

400

Lastpage

405

Abstract

Physical and generic models that analytically couple the array architecture of CMOS SRAMs with the wire lengths and fan-outs along critical paths to decode and sense data are reported. Verified to be accurate with published SRAMs, these models enable the design of optimal array architectures to minimize total access time by balancing communication distance limited wire delays with fan-out and area limited gate delays

Keywords

CMOS memory circuits; SRAM chips; logic design; memory architecture; CMOS SRAM circuit design; CMOS SRAMs; array architecture; communication distance; gate delays; optimal array architectures; wire delays; Analytical models; CMOS technology; Capacitance; Circuit synthesis; Decoding; Delay effects; Integrated circuit interconnections; Random access memory; Semiconductor device modeling; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-7695-1200-3

Type

conf

DOI

10.1109/ICCD.2001.955058

Filename

955058

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1603480