Title :
Interconnect-centric array architectures for minimum SRAM access time
Author :
Bhavnagarwala, Azeez J. ; Kosonocky, Stephen ; Meindl, James D.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
Physical and generic models that analytically couple the array architecture of CMOS SRAMs with the wire lengths and fan-outs along critical paths to decode and sense data are reported. Verified to be accurate with published SRAMs, these models enable the design of optimal array architectures to minimize total access time by balancing communication distance limited wire delays with fan-out and area limited gate delays
Keywords :
CMOS memory circuits; SRAM chips; logic design; memory architecture; CMOS SRAM circuit design; CMOS SRAMs; array architecture; communication distance; gate delays; optimal array architectures; wire delays; Analytical models; CMOS technology; Capacitance; Circuit synthesis; Decoding; Delay effects; Integrated circuit interconnections; Random access memory; Semiconductor device modeling; Wire;
Conference_Titel :
Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-7695-1200-3
DOI :
10.1109/ICCD.2001.955058
