Title :
Architectural enhancements for fast subword permutations with repetitions in cryptographic applications
Author :
McGregor, John P. ; Lee, Ruby B.
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
We propose two new instructions, swperm and sieve, that can be used to efficiently complete an arbitrary bit-level permutation of an n-bit word with or without repetitions. Permutations with repetitions are rearrangements of an ordered set in which elements may replace other elements in the set; such permutations are useful in cryptographic algorithms. On a 4-way superscalar processor, an arbitrary 64-bit permutation with repetitions of 1-bit subwords can be completed in 11 instructions and only 4 cycles using the two proposed instructions. For subwords of size 4 bits or greater, an arbitrary, permutation with repetitions of a 64-bit register can be completed in a single cycle using a single swperm instruction. This improves upon previous permutation instruction proposals that require log(r) sequential instructions to permute r subwords of a 64-bit word without repetitions. Our method requires fewer instructions to permute 4-bit or larger subwords packed in a 64-bit register and fewer execution cycles for 1-bit subwords on wide superscalar processors
Keywords :
cryptography; delays; parallel architectures; table lookup; 64-bit register; arbitrary bit-level permutation; architectural enhancements; cryptographic algorithms; n-bit word; permutation instruction; sequential instructions; sieve; superscalar processor; swperm; Arithmetic; Cellular neural networks; Cryptography; Data security; Microprocessors; Proposals; Registers; Software performance; Sun; Table lookup;
Conference_Titel :
Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-7695-1200-3
DOI :
10.1109/ICCD.2001.955065