Title :
An analytical model for trace cache instruction fetch performance
Author :
Hossain, Afzal ; Pease, Daniel J.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Syracuse Univ., NY, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
This paper presents an analytical model of instruction fetch performance of a trace cache. This paper also presents an analytical model of miss rate of a trace cache. These models can be used to analyze performance and behavior of a microarchitecture of a processor. These models are implemented in a new microarchitecture tool Tulip. Performances of several benchmark programs based on Tulip are also presented in this paper
Keywords :
cache storage; instruction sets; software performance evaluation; Tulip; analytical model; benchmark programs; microarchitecture; trace cache instruction fetch performance; Accuracy; Analytical models; Cache memory; Decoding; Delay; Electronic mail; Hardware; Microarchitecture; Performance analysis;
Conference_Titel :
Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-7695-1200-3
DOI :
10.1109/ICCD.2001.955069
