A comparative analysis of 3D-IC partitioning schemes for asynchronous circuits

Author

Caley, Landon ; Chien-Wei Lo ; Sabado, Francis ; Jia Di

Author_Institution

Comput. Sci. & Comput. Eng. Dept., Univ. of Arkansas Fayetteville, Fayetteville, AR, USA

fYear

2014

fDate

28-30 May 2014

Firstpage

1

Lastpage

4

Abstract

In an attempt to further extend Moore´s Law, circuit designers are turning to three-dimensional integrated circuit (3D-IC) design. However, stacking active devices presents new design challenges, the most notable being thermal dissipation. When paired with a delay-insensitive asynchronous circuit design technique such as NULL Convention Logic (NCL), the two technologies unite to solve the inherent weaknesses of each other. As part of the 3D-IC design process, a circuit must be partitioned evenly between the stacked wafers. This study presents three strategies to split an NCL circuit into two die, in an attempt to discover the optimal partitioning method for asynchronous circuits. Analysis is done on total interconnect length, number of thru-silicon vias required, and circuit area.

Keywords

asynchronous circuits; integrated circuit design; logic partitioning; three-dimensional integrated circuits; 3D IC partitioning; NULL convention logic; asynchronous circuits; delay insensitive asynchronous circuit design technique; interconnect length; thermal dissipation; three dimensional integrated circuit design; Asynchronous circuits; Integrated circuit interconnections; Logic gates; Pipelines; Stacking; Three-dimensional displays; Through-silicon vias; 3D-IC; Delay-Insensitive Asynchronous Logic; NULL Convention Logic; Partitioning;

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design & Technology (ICICDT), 2014 IEEE International Conference on

Conference_Location

Austin, TX

Type

conf

DOI

10.1109/ICICDT.2014.6838586

Filename

6838586