Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations

Prior art on Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN) shows their importance for digital system reliability. Reaction-diffusion models align poorly with deca-nanometer dimension experiments. Modern atomistic models capture time-zero/-dependent effects but are complicated and constrained by system memory. We propose an atomistic BTI/RTN transient simulator that can be massively threaded across any many-core platform with a hypervisor. Compared to a commercial reference we achieve x7 maximum speedup with no accuracy degradation and simulate circuits with more than 100,000 transistors. We deterministically inspect the initial stages of circuit operation, correlate delay effects with the logic depth and hint towards optimal design and simulation practices.