DocumentCode
1604236
Title
Timing characterization of dual-edge triggered flip-flops
Author
Nedovic, Nikola ; Aleksic, Marko ; Oklobdzija, Vojin G.
Author_Institution
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
fYear
2001
fDate
6/23/1905 12:00:00 AM
Firstpage
538
Lastpage
541
Abstract
A novel timing characterization for dual-edge triggered flip-flops is presented. This characterization takes into account the real overhead taken from the clock cycle by the flip-flops. Our study shows the correctness of these new metrics when compared against data-to-output delay. An example of the proposed delay characterization and comparison with conventional (data-to-output) metrics for dual-edge flip-flop design is given
Keywords
flip-flops; logic CAD; timing; clock cycle; data-to-output delay; data-to-output metrics; delay characterization; dual-edge flip-flop design; dual-edge triggered flip-flops; set-up time requirements; simple timing characterization; timing characterization; Clocks; Delay; Energy consumption; Flip-flops; Frequency; Jitter; Logic; Timing; Uncertainty; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design, 2001. ICCD 2001. Proceedings. 2001 International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-7695-1200-3
Type
conf
DOI
10.1109/ICCD.2001.955087
Filename
955087
Link To Document