Single-ended sub-threshold finfet 7T SRAM cell without boosted supply

Author

Kushwah, C.B. ; Vishvakarma, Santosh Kumar ; Dwivedi, D.

Author_Institution

Electr. Eng., IIT Indore, Indore, India

fYear

2014

fDate

28-30 May 2014

Firstpage

1

Lastpage

4

Abstract

The proposed novel FinFET 7T cell involves the breaking-up of feedback between the true storing nodes that enhances the writability of the cell at ultra-low voltage (ULV) power supply without boosted supply and write assist at 20nm technology node. Proposed 7T achieves improved hold static noise margin (HSNM) as compared to the conventional upsized 5T(U5T) cell. The write trip point (WTP) is 16.2% lower than the U5T WTP at 100mV. The read power consumption is reduced by 13.7% with similar write power consumption of U5T. The read decoupling and feedback cutting makes proposed 7T more immune to process variations in sub-threshold regime.

Keywords

DRAM chips; MOSFET circuits; circuit feedback; integrated circuit noise; low-power electronics; power consumption; HSNM; U5T cell; ULV; WTP; feedback cutting; hold static noise margin; process variations; read decoupling; read power consumption; single-ended sub-threshold FinFet 7T SRAM cell; size 20 nm; true storing nodes; ultra-low voltage power supply; upsized 5T cell; voltage 100 mV; write power consumption; write trip point; Circuit stability; Delays; FinFETs; SRAM cells; Stability analysis; FinFET; HSNM; SRAM; WTP; sub-threshold; ultra-low power (ULP); writability;

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design & Technology (ICICDT), 2014 IEEE International Conference on

Conference_Location

Austin, TX

Type

conf

DOI

10.1109/ICICDT.2014.6838593

Filename

6838593