Title :
Design layout optimization in the presence of proximity-dependent stress effects
Author :
Sultan, Ahmed ; Ramzan, Rashad ; Wristers, Derick
Author_Institution :
Dept. of Electr. Eng., United Arab Emirates Univ., Al Ain, United Arab Emirates
Abstract :
In this paper, we present Minimized Layout Effect (MINLAYEF) guidelines for reducing the layout and process variations in critical analog circuits. We also present digital design guidelines to minimize the effect of process variations by eliminating stress sources. We also propose a layout for a reference device for a dual stress liner (DSL) device architecture to improve the accuracy of simulations. Si results from circuit layout designed with and without layout guidelines are also presented.
Keywords :
analogue circuits; circuit optimisation; elemental semiconductors; integrated circuit layout; proximity effect (lithography); silicon; stress effects; DSL device architecture; MINLAYEF guidelines; Si; circuit layout; critical analog circuits; design layout optimization; digital design guidelines; dual stress liner device architecture; minimized layout effect; process variation effect; proximity-dependent stress effects; stress source elimination; DSL; Degradation; Fingers; Guidelines; Layout; MOS devices; Stress; DSL; Layout guidelines; Stress proximity effects;
Conference_Titel :
IC Design & Technology (ICICDT), 2014 IEEE International Conference on
Conference_Location :
Austin, TX
DOI :
10.1109/ICICDT.2014.6838594
