Verilog - A Implementation of ICS Model for PD SOI Devices

We present a Verilog-A implementation of an Improved Charge Sheet Model (ICSM) for PD SOI MOSFETs. This model is a physical and continuous compact model for deep-submicron transistors focused in an accurate description of high order derivatives, in order to obtain good approximation of the harmonic distortion behavior. The implementation of the model, using Verilog-A language, allows analog circuit designer simulate their PD SOI design in SPICE circuit simulators, expecting reliable results.