Hardware support for backward error recovery

We propose a hardware support structure for the implementation of backward error or recovery mechanisms as applied to dependable systems. The proposed design moves on from previous hardware support systems by considering all phases of error recovery, not simply the saving of critical state information. The proposed architecture makes use of programmable logic devices to provide a flexible and efficient implementation of the software constructs proposed for error recovery. The system under consideration consists of a distributed parallel processing system with cooperating processes.