Robust bias temperature instability refresh design and methodology for memory cell recovery

We propose a robust hardware based methodology for efficient bias temperature instability recovery for SRAM designs. The methodology exploits existing memory infrastructure to enable fast and reliable cell data flipping. Most importantly, the proposed methodology allows for localized write back and inverted read operations thereby eliminating the need for explicit inversion. A detailed analysis illustrates minimal overhead in terms of both control signal and delays for the proposed design. The impact of supply voltage, process variations and bitline loading is evaluated. A leakage monitor is proposed to initiate and trigger the refresh.