• DocumentCode
    1604713
  • Title

    Reducing the cost of branches by using registers

  • Author

    Davidson, Jack W. ; Whalley, David B.

  • Author_Institution
    Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
  • fYear
    1990
  • Firstpage
    182
  • Lastpage
    191
  • Abstract
    In an attempt to reduce the number of operand memory references, many RISC (reduced-instruction-set-computer) machines have 32 or more general-purpose registers (e.g. MIPS, ARM, Spectrum, 88 K). Without special compiler optimizations, such as inlining or interprocedural register allocation, it is rare that a computer will use a majority of these registers for a function. The authors explore the possibility of using some of these registers to hold branch target addresses and the corresponding instruction at each branch target. To evaluate the effectiveness of this scheme, two machines were designed and emulated. One machine had 32 general-purpose registers used for data references, while the other machine had 16 data registers and 16 registers used for branching. The results show that using registers for branching can effectively reduce the cost of transfers of control
  • Keywords
    computer architecture; instruction sets; RISC; branch target addresses; branching cost reduction; branching overhead reduction; data references; general-purpose registers; operand memory references; reduced-instruction-set-computer; Added delay; Assembly; Computer science; Costs; Decoding; Optimizing compilers; Pipelines; Prefetching; Reduced instruction set computing; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture, 1990. Proceedings., 17th Annual International Symposium on
  • Conference_Location
    Seattle, WA
  • Print_ISBN
    0-8186-2047-1
  • Type

    conf

  • DOI
    10.1109/ISCA.1990.134524
  • Filename
    134524