Variability of planar Ultra-Thin Body and Buried oxide (UTBB) FDSOI MOSFETs

We show that planar Fully Depleted Silicon-On-Insulator (FDSOI) technology allows improving the threshold voltage V_T variability of CMOS devices in comparison to standard bulk CMOS devices. Moreover, integrated on Ultra-Thin Body and Buried oxide (UTBB), it enables the use of standard power management techniques (Reverse or Forward Back Biasing) without V_T variability penalty. Drain current I_D mismatch variations (σ_ID) are found to be correlated with both threshold voltage (V_T) and ON-state resistance (R_ON) fluctuations. Additionally, the impact of R_ON and V_T variations is significantly reduced by their advantageous correlation, while σ_ΔVT remains the major σ_ID contributor. Finally, we demonstrate that SiGe channel could be used to improve global V_T variability of short channel pMOS devices in addition to enhanced performances.