Assessing device reliability through atomic-level modeling of material characteristics

Electrical characteristics of the advanced logic and memory devices, which incorporate nano-thin layers of dielectric materials in their gate dielectric stacks, are sensitive to even extremely small concentrations of electrically active defects. Conventional empirical reliability models, which heavily rely on statistical data sets, demonstrate limited capability to predict the parameters drift in these highly scaled devices ultimately leading to larger performance margins and, correspondingly, lower manufacturing yield. An alternative approach we employ is to link the structural and electrical characteristics of these multicomponent stacks to identify critical characteristics of the electrically active defects and, then, use the developed defect library to predictively model the gate stack electrical properties and their evolution under device operation conditions. This modeling scheme is implemented in the software package simulating a variety of electrical measurements.