DocumentCode
16054
Title
Petri Net-Based FTL Architecture for Parametric WCET Estimation via FTL Operation Sequence Derivation
Author
Jonghun Yoo ; Jaesoo Lee ; Seongsoo Hong
Author_Institution
Dept. of Electr. & Comput. Eng., Seoul Nat. Univ., Seoul, South Korea
Volume
62
Issue
11
fYear
2013
fDate
Nov. 2013
Firstpage
2238
Lastpage
2251
Abstract
A flash translation layer (FTL) provides file systems with transparent access to NAND flash memory. Although many applications running on it require real-time guarantees, it is difficult to provide tight worst case execution time (WCET) bounds with conventional static WCET analysis since an FTL exhibits a large variance in execution time depending on its runtime state. Parametric WCET analysis could be an effective alternative but it is also challenging to formulate a parametric WCET function for an FTL program because traditional FTL architecture does not properly model the runtime availability of flash resources in its code structure. To overcome such a limitation, we propose Petri net-based FTL architecture where a Petri net explicitly specifies dependencies between FTL operations and the runtime resource availability. It comes with an FTL operation sequencer that derives at runtime the shortest sequence of FTL operations for servicing an incoming FTL request under the current resource availability. The sequencer computes the WCET of the request by merely summing the WCETs of only those FTL operations in the sequence. Our experimental results show the effectiveness of our FTL architecture. It allowed for tight WCET estimation that yielded WCETs shorter by a factor of 54 than statically analyzed ones.
Keywords
Petri nets; flash memories; logic gates; program diagnostics; software architecture; FTL operation sequence derivation; FTL program; NAND flash memory; Petri net-based FTL architecture; code structure; execution time; file systems; flash resources; flash translation layer; parametric WCET analysis; parametric WCET estimation; parametric WCET function; runtime resource availability; static WCET analysis; transparent access; worst case execution time; Petri nets; Real-time systmes; Software architecture; Real-time and embedded systems; performance modeling and prediction; software architectures;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.2012.114
Filename
6212444
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