VLSI architecture for very high resolution scalable video coding using the virtual zerotree

In this paper, we present a hardware architecture for very high resolution (VHR) scalable video coding using the virtual zerotree (VZT) algorithm, a variant of the embedded zerotree wavelet (EZW) algorithm. The VZT architecture is regular and modular and is suitable for VLSI implementation. The output of the architecture is a data stream containing the virtual map, significance map and successive-approximation quantization symbols of the VZT algorithm. The approach is based on an efficient scheme to determine ancestor-descendant relationships in the wavelet coefficient data stream by rearrangement of the data stream for simpler VLSI implementation. The approach uses the sign-magnitude binary representation of the rearranged wavelet coefficients to form a single bit data stream as the input into the architecture. The coding and quantization for the VZT algorithm are formulated in view of the single bit data stream input and the corresponding VLSI architecture to implement the formulated requirements is presented