Title :
A compact IDCT processor for HDTV applications
Author :
Chang, Tian-Sheuan ; Guo, Jiun-In ; Jen, Chein-Wei
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
6/21/1905 12:00:00 AM
Abstract :
This paper presents a compact IDCT processor for HDTV applications by using cyclic convolution and hardwired multipliers. By properly arranging the input sequence, we formulate IDCT into cyclic convolution that is regular and suitable for VLSI implementation. The hardwired multipliers that implement multiplications with scaled IDCT coefficients are optimized by common subexpression techniques. Based on these techniques, our proposed design costs 7504 gates plus 1024 bits of memory with 100M pixels/sec throughput
Keywords :
data compression; discrete cosine transforms; high definition television; video coding; HDTV applications; compact IDCT processor; cyclic convolution; hardwired multipliers; video compression; Convolution; Costs; Decoding; Discrete cosine transforms; Educational institutions; HDTV; Hardware; Throughput; Very large scale integration; Video compression;
Conference_Titel :
Signal Processing Systems, 1999. SiPS 99. 1999 IEEE Workshop on
Conference_Location :
Taipei
Print_ISBN :
0-7803-5650-0
DOI :
10.1109/SIPS.1999.822320
