DocumentCode
1605863
Title
Power efficient instruction cache for wide-issue processors
Author
Badulescu, Ana-Maria ; Veidenbaum, Alexander
Author_Institution
Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
fYear
2001
fDate
6/23/1905 12:00:00 AM
Firstpage
12
Lastpage
15
Abstract
The paper focuses on reducing power in instruction cache by eliminating the fetching of instructions that are not needed from a cache line. We propose a mechanism that predicts which instructions are going to be used out of a cache line before that line is fetched into the instruction buffer. The average instruction cache power savings obtained by using our fetch predictor is 22% for SPEC95 benchmark suite
Keywords
cache storage; instruction sets; memory architecture; power consumption; SPEC95 benchmark suite; average instruction cache power savings; fetch predictor; instruction buffer; instruction cache; instruction fetching; power efficient instruction cache; power reduction; wide-issue processors; Cache memories;
fLanguage
English
Publisher
ieee
Conference_Titel
Innovative Architecture for Future Generation High-Performance Processors and Systems, 2001
Conference_Location
Maui, HI
ISSN
1537-3223
Print_ISBN
0-7695-1309-3
Type
conf
DOI
10.1109/IWIA.2001.955192
Filename
955192
Link To Document