Design and implementation of enhanced crossbar CIOQ switch architecture

Currently, combined input output queued (CIOQ) switches are being considered for high performance switch architectures. This is due to their ability to achieve high throughput and emulate output queued switch performance with a small speedup factor of 4 or 5. The paper presents the design and VLSI implementation of a 16×16 cell based CIOQ switch with enhanced crossbars to provide a speedup of 4 while operating the switch fabric at the line rate and memories at half the line rate. We describe the implementation of this architecture in VLSI using 0.18 micron CMOS standard-cell technology. We report on the design complexity and discuss implementation results. This architecture can handle a line rate of 622 Mbps. The distributed cell scheduling and cell queueing and dequeueing allows this architecture to be scaled to a large number of inputs and outputs.