DocumentCode
1606154
Title
A method to evaluate the skew by data dependent gate loading in VLSI system
Author
Jiang, Yanfeng ; Zhang, Xiaobo ; Yang, Bing
Author_Institution
Dept. of Microelectron., North China Univ. of Technol., Beijing, China
fYear
2009
Firstpage
547
Lastpage
550
Abstract
In this paper, the skew by data dependent gate loading has been analysized. A method based on the concept of MOS parametric capacitance has been proposed. According to different data dependent of the MOS transistor, including transient channel charge and Miller effects, the values of capacitance in different data loadings have been extracted. Two clock tree routes have been analyzed by using the gate loading effect. Results revealed that the simulation result including the gate loading approaches to the actual ones closely.
Keywords
MOSFET; VLSI; MOS parametric capacitance; MOS transistor; VLSI system; clock tree route analysis; data dependent gate loading; skew evaluation; Capacitance; Clocks; Data mining; Delay effects; Educational institutions; Educational technology; Integrated circuit interconnections; Microelectronics; Timing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Asian Control Conference, 2009. ASCC 2009. 7th
Conference_Location
Hong Kong
Print_ISBN
978-89-956056-2-2
Electronic_ISBN
978-89-956056-9-1
Type
conf
Filename
5276380
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