A fuzzy neural network chip based on systolic array architecture

Author

Chen, Jiahn-Jung ; Kuo, Yau-Hwang ; Kao, Cheng-I

Author_Institution

Inst. of Inf. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

1992

Firstpage

577

Lastpage

580

Abstract

A neural network model using a fuzzy classification concept, called FNN, is proposed. The design of an ASIC that implements that FNN model is presented. The chip architecture is based on a one-dimensional systolic array architecture, which provides a low-cost and high-performance parallel inference scheme. The high-level synthesis technique is adopted to design the ASIC, and VHSIC hardware description language (VHDL) is used to model it at the behavior domain

Keywords

application specific integrated circuits; fuzzy logic; inference mechanisms; neural chips; specification languages; systolic arrays; ASIC; FNN; VHSIC hardware description language; behavior domain; chip architecture; fuzzy classification concept; fuzzy neural network chip; high-level synthesis technique; parallel inference scheme; systolic array architecture; Application specific integrated circuits; Backpropagation; Fuzzy logic; Fuzzy neural networks; High level synthesis; Knowledge representation; Neural networks; Pattern classification; Pattern recognition; Systolic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International

Conference_Location

Rochester, NY

Print_ISBN

0-7803-0768-2

Type

conf

DOI

10.1109/ASIC.1992.270195

Filename

270195