Novel architecture for hardware efficient FPGA implementation of real time configurable “variable point FFT” using NIOS II™

Signal processor forms the heart of the radar subsystems and is responsible for the discernment of targets from interfering clutter and improving the SNR of the received signal for better detection of targets. Doppler filter bank is one of the modules used in signal processor to extract the Doppler information from the target, to improve the SNR and it also provides information regarding target velocity. In this paper we present a novel and simple architecture to perform hardware efficient real time configurable ldquovariable point FFTrdquo using NIOSIItrade. The architecture can be used in multiple scan rate radars to reduce the resource utilization which can be used for other additional processing features. The architecture is generic in nature and can be extended to other platforms besides FPGA.