2T-FN eNVM with 90 nm Logic Process for Smart Card

We have suggested 2T-Flash cell design methodology to achieve high performance even at sub-90 nm technology nodes for embedded SOC applications (eNVM) and demonstrated by 8x8 array cells. By adopting two different transistors´ channel width and boosted gate biasing and new tunnel oxide, current performance increase more than 20%. The fabricated devices also meet 500K endurance and 10 years retention characteristics for smart card application.