Design and synthesis of an Intel 80C51-compatible microprocessor optimized for reduced instruction-time execution

A new architecture has been developed to reduce the instruction-time execution of a microprocessor compatible with the Intel 80C51. This higher performance is achieved by executing all instructions in a minimum number of clock cycles. Dual edge-triggered flip-flops, selective clocking of components, and a hardware-oriented structure are incorporated to produce a processor which has better throughput and lower power dissipation than the Intel 80C51. The new architecture focuses on combining increased performance with low power dissipation